Circuit for generating a high-frequency oscillation in a specified frequency band

ABSTRACT

An oscillator circuit for generating a high-frequency electromagnetic oscillation, comprises:—an amplifier configuration with at least one input and at least one output,—an oscillator crystal connected to at least one of the outputs of the amplifier configuration,—a bandpass filter configuration, which is connected, with at least one input, to the oscillator crystal and the at least one output of the amplifier configuration connected to the oscillator crystal, and back coupled, with at least one output, to the input, or at least one of the inputs, of the amplifier configuration. Through dimensioning of the amplitude-frequency characteristic and/or the phase-frequency characteristic of the band-pass filter configuration as a function of the amplitude-frequency characteristic and the phase-frequency characteristic of the amplifier configuration and the crystal oscillator, the oscillation condition is hereby fulfilled exclusively for a selected harmonic of the oscillator crystal, and the high-frequency, electromagnetic oscillation formed by this selected harmonic of the oscillator crystal is available at the output of the bandpass filter configuration. This oscillator circuit is simply constructed and enables operation that is at least largely non-susceptible to interference.

The invention relates to an oscillator circuit for generating ahigh-frequency electromagnetic oscillation.

Known from the monograph “Halbleiter-Schaltungstechnik” (Semiconductorcircuitry) by U. Tietze and Ch. Schenk, 8^(th) edition, Springer-Verlag,1986, section 15.2.2, pp 450, 451, is a Pierce oscillator, which isdesigned as a fundamental frequency oscillator with an oscillatorcrystal. In a fundamental frequency oscillator of this kind, the circuitconfiguration oscillates on the fundamental wave of the oscillatorcrystal.

It is further known from the above-cited monograph“Halbleiter-Schaltungstechnik”, section 15.2.3, pp 452 to 454, thatoscillator crystals are difficult to produce for frequencies above 30MHz. As a solution for generating high frequencies of this kind withcrystal stability, it is proposed therein to excite an oscillatorcrystal on a harmonic wave, since, in the case of odd-order harmonics,an oscillator crystal also possesses resonance points. According to thecited document, in order to excite a crystal on a harmonic wave, anamplifier is required, the gain of which has a maximum in the vicinityof the desired frequency. To this end, the use of an additional LCresonant circuit tuned to the desired harmonic wave is proposed. Acorrespondingly modified Hartley oscillator and a Colpitts oscillatorare proposed.

The proposed oscillators have the disadvantage that they are equippedwith an LC resonant circuit. A resonant circuit of this kind isrelatively expensive to produce and, in comparison with modernintegrated semiconductor circuits, requires a great deal of space. Inaddition, it is a component that has to be assigned externally to anintegrated semiconductor circuit of this kind, which is not desirableeither, on grounds of space and cost.

Strictly speaking, in an oscillator of this kind, any undesired resonantfrequency, but at least every resonant frequency of the oscillatorcrystal that is lower than the desired frequency of the oscillator, alsohas to be attenuated by a separate LC series resonant circuit, i.e.when, for example, the fifth harmonic is operated, the fundamental waveand the third harmonic have to be attenuated by an appropriately tunedLC series resonant circuit. Therefore, only harmonic oscillators withfundamental wave suppression that are operated on the third harmonic arecommonly encountered in practice.

In circuit configurations containing, in mixed construction, circuitstages for processing analog and digital signals, most crystaloscillators produced in integrated CMOS semiconductor technology show asharp increase in instabilities, also known as “jitter”, with increasinginterference in respect of the semiconductor substrate potential or thesupply voltage, both of which kinds may be caused by e.g. digitalsignals in the integrated circuit. If oscillators of this kind are usedto generate a clock signal, the cited instabilities arise in this clocksignal and cannot be completely eliminated by a downstream phase-lockedloop (PLL).

It is an object of the invention to create an oscillator circuit thathas a simple structure and enables operation that is at least largelynon-susceptible to the above-described interference.

The object is achieved in accordance with the invention by means of anoscillator circuit for generating a high-frequency, electromagneticoscillation, comprising:

-   -   an amplifier configuration with at least one input and at least        one output,    -   an oscillator crystal connected to at least one of the outputs        of the amplifier configuration,    -   a bandpass filter configuration, which is connected, with at        least one input, to the oscillator crystal and the at least one        output of the amplifier configuration connected to the        oscillator crystal, and back coupled, with at least one output,        to the input, or at least one of the inputs, of the amplifier        configuration,        wherein, through dimensioning of the amplitude-frequency        characteristic and/or the phase-frequency characteristic of the        bandpass filter configuration as a function of the        amplitude-frequency characteristic and the phase-frequency        characteristic of the amplifier configuration and the oscillator        crystal, the oscillation condition is fulfilled exclusively for        a selected harmonic of the oscillator crystal, and the        high-frequency, electromagnetic oscillation formed by this        selected harmonic of the oscillator crystal is available at the        output of the bandpass filter configuration.

The oscillator circuit in accordance with the invention enables thegeneration of a selected harmonic of the oscillator crystal (alsodesignated overtone oscillation) without a component to be assignedexternally to an oscillator circuit of this kind, constructed as anintegrated semiconductor circuit, in particular without additionalexternal components on the terminals provided for connection of theoscillator crystal to the oscillator circuit, i.e. the crystal terminalsof the oscillator circuit. In many cases, the direct generation of anoscillator crystal harmonic of this kind and its use as a clock signalin signal processing configurations to be used with the oscillatorcircuit in accordance with the invention renders frequency synthesis bymeans of PLL from a lower crystal oscillator frequency unnecessary. Incases in which a clock signal is to be generated without PLL, bycomparison with an oscillator crystal of the same frequency (alsodesignated a fundamental wave crystal), which is operated in itsfundamental mode and generates a corresponding clock signal, theoscillator circuit in accordance with the invention enables a morecost-effective use of an oscillator crystal (also designated an overtonecrystal) operated on a harmonic of this kind.

In addition, the oscillator circuit in accordance with the inventionenables an oscillation generation, and thereby a clock signalgeneration, which is at least largely free of the instabilities known as“jitter” even in the case of strong interference of the semiconductorsubstrate potential or the supply voltage in an oscillator circuit ofthis kind, constructed as an integrated semiconductor circuit. Theoscillator circuit in accordance with the invention is thereforeespecially suitable for use in integrated semiconductor circuits whichcontain, in mixed construction, circuit stages for processing analog anddigital signals.

In an advantageous further embodiment of the oscillator circuit inaccordance with the invention, the amplifier configuration is designedwith, in each case, at least one pair of at least virtually symmetricalinputs and outputs (differential inputs and outputs) for processingelectromagnetic oscillations (known as differential signals), operatedat least virtually symmetrically relative to a first referencepotential. Preferably selected as the first reference potential herebyis a direct-current operating point of the amplifier configuration. Thedirect-current operating points of the amplifier configuration and ofthe oscillator circuit as a whole preferably correspond hereby.

In another further embodiment of the oscillator circuit in accordancewith the invention, the amplifier configuration comprises a differentialamplifier circuit, which is equipped with two field effect transistorscoupled at their source terminals, the gate terminals of which are eachcoupled with one of the differential inputs of the amplifierconfiguration, wherein a drain terminal of each field effect transistorforms one of the differential outputs of the amplifier configuration,each of which is further coupled, via a load path, each of whichcomprises at least one field effect transistor, designated an outputload transistor, with a terminal carrying a second reference potential.A ground potential is hereby preferably selected as the second referencepotential.

The amplifier configuration hereby preferably comprises acontrol-voltage generation stage for generating a control voltage, whichis supplied to gate terminals of the output load transistors. Inparticular, the control-voltage generation stage herein comprises aseries circuit comprising a constant current source and a field effecttransistor bridged between its drain terminal and gate terminal.

An advantageous further embodiment of the oscillator circuit inaccordance with the invention is further characterized in that theamplifier configuration comprises an operating-point regulating stagewith three field effect transistors, a first of which is disposed in thefirst load path and a second of which is disposed in the second loadpath, each connected in series with the output load transistor there,and a third of which is connected in series with the series circuitcomprising the constant current source and field effect transistor ofthe control-voltage generation stage, wherein a gate terminal of thefirst of the three field effect transistors of the operating-pointregulating stage is connected to a first of the differential outputs ofthe amplifier configuration, wherein a gate terminal of the second ofthe three field effect transistors of the operating-point regulatingstage is connected to a second of the differential outputs of theamplifier configuration, wherein a gate terminal of the third of thethree field effect transistors of the operating-point regulating stageis connected to the gate terminals of the output load transistors andwherein the three field effect transistors of the operating-pointregulating stage are routed, with their source terminals, to theterminal carrying the second reference potential.

In accordance with another advantageous embodiment of the oscillatorcircuit in accordance with the invention, the amplifier configurationcomprises an offset compensation device comprising, in each case, ahigh-pass circuit between:

-   -   each of the differential inputs of the amplifier configuration,    -   the gate terminal of the field effect transistor of the        differential amplifier circuit comprising the amplifier        configuration that is coupled with this differential input,    -   the differential output formed by the drain terminal of said        field effect transistor. The limiting frequency of this        high-pass circuit is small as compared with the frequency        operating range of the oscillator circuit.

In a preferred further embodiment of this oscillator circuit inaccordance with the invention, each of the high-pass circuits contains acapacitor, via which the differential input of the amplifierconfiguration is coupled with the gate terminal of the field effecttransistor of the differential amplifier circuit comprising theamplifier configuration, and each of the high-pass circuits furthercontains an ohmic resistance element, via which the gate terminal of thefield effect transistor of the differential amplifier circuit comprisingthe amplifier configuration is coupled with the differential output ofthe amplifier configuration formed by the drain terminal of this fieldeffect transistor.

In accordance with another embodiment of the oscillator circuit inaccordance with the invention, the amplifier configuration is coupledwith an auxiliary starting circuit, by means of which, during apredetermined period when the oscillator circuit is put into operation,a differential voltage is supplied to the gate terminals of the fieldeffect transistors, coupled at their source terminals, of thedifferential amplifier circuit comprising the amplifier configuration.

The auxiliary starting circuit preferably comprises:

-   -   a first field effect transistor, which is disposed between the        gate terminal of a first of the field effect transistors,        coupled at their source terminals, of the differential amplifier        circuit comprising the amplifier configuration, and a third        reference potential;    -   a second field effect transistor, which is disposed between the        gate terminal of a second of the field effect transistors,        coupled with their source terminals, of the differential        amplifier circuit comprising the amplifier configuration, and        the third reference potential;    -   a start-signal input for supplying an at least largely        pulse-shaped or step-shaped start signal when the oscillator        circuit is put into operation;    -   a delay stage;        wherein the start-signal input is directly coupled with a gate        terminal of the first field effect transistor of the auxiliary        starting circuit and, via the delay stage, with a gate terminal        of the second field effect transistor of the auxiliary starting        circuit. A supply voltage emitted at a supply-voltage terminal        is hereby preferably selected as the third reference potential.

In another advantageous embodiment of the oscillator circuit inaccordance with the invention, the oscillator crystal takes the form ofa two-terminal network and is connected with, in each case, one of itsterminals to, in each case, one of the outputs of a pair of differentialoutputs of the amplifier configuration, in order to supply anelectromagnetic oscillation emitted by the amplifier configuration inthe form of a differential signal.

In another advantageous embodiment of the oscillator circuit inaccordance with the invention, the bandpass filter configuration isdesigned with, in each case, at least one pair of at least virtuallysymmetrical input and outputs (known as differential inputs and outputs)for processing electromagnetic oscillations (known as differentialsignals), operated at least virtually symmetrically relative to a fourthreference potential. Preferably selected as this fourth referencepotential is a direct-current operating point of the bandpass filterconfiguration.

The direct-current operating point of the bandpass filter configurationhereby preferably corresponds with that of the oscillator circuit as awhole. So, in this case, the fourth reference potential of the bandpassfilter configuration resembles the first reference potential of theamplifier configuration, and thereby the direct-current operating pointof the oscillator circuit as a whole.

In accordance with an advantageous further embodiment of the oscillatorcircuit in accordance with the invention, the bandpass filterconfiguration is connected, with at least one pair of its differentialinputs, to at least the pair of differential outputs of the amplifierconfiguration that are connected to the terminals of the oscillatorcrystal, and, with at least one pair of its differential outputs, to atleast one pair of differential inputs of the amplifier configuration.

In accordance with an advantageous further embodiment of this oscillatorcircuit in accordance with the invention, the bandpass filterconfiguration is designed with a cascode connection of at least twobandpass stages of low quality. It is true that a design with only onebandpass stage of higher quality would also be possible. However,bandpass stages of this kind exhibit a higher power consumption thanthose of low quality. In addition, typical production tolerances ofintegrated semiconductor circuits mean that high-quality bandpass stagesare more difficult to produce with the required accuracy while adheringto the mid-frequency of the bandpass filter configuration. Production istherefore simplified and the power requirement of the oscillator circuitis reduced by said preferred development.

In particular, the bandpass stages are hereby designed, in anadvantageous manner, each with a differential amplifier circuit havingtwo field effect transistors coupled at their source terminals, and withone pair of differential inputs and one pair of differential outputs,wherein each one of the differential inputs is coupled, via one of thehigh-pass circuits, with one of the gate terminals of one of the fieldeffect transistors, and each one of the drain terminals of the fieldeffect transistors forms one of the differential outputs of the bandpassstages, each of which drain terminal is further connected, via one ofthe low-pass circuits, to a terminal carrying a fifth referencepotential, wherein the differential inputs of a first of the bandpassstages disposed in a cascade connection form the differential inputs ofthe bandpass filter configuration that are connected to the terminals ofthe oscillator crystal, and wherein the differential outputs of a lastof the bandpass stages disposed in a cascade connection form thedifferential outputs of the bandpass filter configuration that areconnected to the differential inputs of the amplifier configuration. Aground potential is preferably selected as the fifth referencepotential. The second reference potential thereby preferably correspondswith the fifth reference potential.

In accordance with an advantageous development of the oscillator circuitin accordance with the invention, the high-pass circuits and/or thelow-pass circuits are designed as RC networks. These may be constructedfor the high frequencies to be generated in integrated semiconductortechnology on a common semiconductor body with the remaining componentsof the oscillator circuit.

The RC networks are preferably equipped with switchable ohmic resistors.A change is thereby possible in the filter characteristic curves of thehigh-pass circuits and/or low-pass circuits constructed, in accordancewith the invention, with said RC networks. In particular, anadvantageous configuration is achieved by means of an additionaltrimming circuit to trim the resistance values of the switchable ohmicresistors in the RC networks with a reference resistor. In many cases, areference resistor of this kind, which is generally disposed outside ofan integrated semiconductor circuit, is present in any event, inparticular for circuit configurations in which analog and digitalsignals are processed jointly, and therefore does not have to beadditionally provided for the oscillator circuit in accordance with theinvention. By means of the trimming circuit, trimming is undertaken, inparticular during or directly following the starting-up of theoscillator circuit, i.e. the powering-up of the supply voltage. Acomparison is hereby made with the precise, external reference resistorand, in the event of discrepancies, the ohmic resistors to be trimmed inthe RC networks are switched to a correct resistance value, as a resultof which production-related fluctuations of these resistance values canbe minimized.

In accordance with another embodiment, the oscillator circuit inaccordance with the invention comprises a converter circuit, coupledwith at least one pair of differential outputs of the bandpass filterconfiguration, for converting the differential signal emitted by thesedifferential outputs into an electromagnetic oscillation operatedasymmetrically relative to the fourth reference potential. As a result,the oscillator circuit can be designed to process differential signals,whereas its output signal, the oscillation to be delivered, can besupplied as an asymmetrically operated signal.

The design of the oscillator circuit in accordance with the inventionfor processing differential signals proves to be an especiallyadvantageous means of reducing susceptibility to interference, asmentioned above, affecting the semiconductor substrate potential or thesupply voltage, which is one cause of said instabilities, designated“jitter”. Through this design of the oscillator circuit, its robustnessto these instabilities is considerably improved.

One advantageous further embodiment of the oscillator circuit inaccordance with the invention is further characterized in that theconverter circuit comprises:

-   -   an input stage designed as a differential amplifier with field        effect transistors coupled at their source terminals, to which        the differential signal to be converted is supplied;    -   a first current mirror stage designed with field effect        transistors coupled via their gate terminals, to mirror a first        differential output signal of the input stage of the converter        circuit into a first intermediate signal;    -   a second current mirror stage designed with field effect        transistors coupled via their gate terminals, to mirror a second        differential output signal of the input stage of the converter        circuit into a second intermediate signal;    -   a third current mirror stage designed with field effect        transistors coupled via their gate terminals, to mirror the        first intermediate signal of the first current mirror stage of        the converter circuit into a third intermediate signal;    -   a subtraction circuit, designed as a current node, to subtract        the second intermediate signal from the third intermediate        signal;    -   an output driver circuit; wherein the third current mirror stage        is further coupled with:    -   an auxiliary switch-on stage with a first cascode field effect        transistor in the input arm of the third current mirror stage;    -   an auxiliary switch-off stage, comprising:    -   a first cascaded stage with a series circuit comprising:        -   a first field effect transistor, which is incorporated into            the second current mirror stage and which is operated,            jointly with the second current mirror stage, by the second            differential output signal of the input stage of the            converter circuit, to emit a fourth intermediate signal,            which is, at least over segments, essentially proportional            to the second intermediate signal;        -   an input transistor, designed as a field effect transistor,            of a fourth current mirror stage;        -   a second cascade field effect transistor in the input arm of            the fourth current mirror stage;    -   the fourth current mirror stage to mirror the fourth        intermediate signal into a fifth intermediate signal and to        supply it to the third current mirror stage, comprising:        -   the input transistor, designed as a field effect transistor,            to supply the fourth intermediate signal;        -   an output transistor, designed as a field effect transistor,            to emit the fifth intermediate signal;            and wherein a cascode bias-voltage generating circuit is            provided to supply a common cascode bias voltage to gate            terminals, coupled together, of the first and second cascode            field effect transistors.

By means of this design of the converter circuit, the edge steepness ofthe output signal of the oscillator circuit, i.e. the oscillation to besupplied by it, can be increased. A further reduction is therebyachieved in the dependence of this output signal on the interference, asmentioned above, affecting the semiconductor substrate potential or thesupply voltage, which is one cause of said instabilities, designated“jitter”.

In a further embodiment of the invention, the cascode-bias-voltagegenerating circuit comprises a series circuit comprising a first and asecond field effect transistor and a constant current source, which isdisposed between a terminal carrying a sixth reference potential and aterminal carrying a seventh reference potential, wherein this firstfield effect transistor is connected, with its drain terminal, to asource terminal of the second field effect transistor, and gateterminals of this first and this second field effect transistor areconnected to each other, to a drain terminal of the second field effecttransistor and to the gate terminals of the first and the second cascodefield effect transistors to supply the common cascode bias voltage. Thesixth reference potential is hereby preferably selected to be equivalentto the second reference potential, and the seventh reference potentialto be equivalent to the third reference potential, so the sixthreference potential preferably corresponds to the ground potential, andthe seventh reference potential preferably corresponds to the supplyvoltage.

The invention will be further described with reference to examples ofembodiments shown in the drawings, to which, however, the invention isnot restricted.

FIG. 1 shows the schematic circuit diagram of a crystal oscillator, inthe form of a Pierce oscillator, for operation with the fundamentaloscillation of the oscillator crystal.

FIG. 2 shows the schematic circuit diagram of a crystal oscillator, inthe form of a Pierce oscillator, for operation with a harmonicoscillation of the oscillator crystal and suppression of the fundamentaloscillation.

FIG. 3 shows a schematic circuit diagram of one example of embodiment ofan oscillator circuit in accordance with the invention.

FIG. 4 shows an equivalent circuit diagram of a fundamental-frequencycrystal.

FIG. 5 shows an equivalent circuit diagram of an overtone crystal.

FIG. 6 shows a schematic circuit diagram of one example of embodiment ofa simple amplifier configuration in an oscillator circuit in accordancewith the invention.

FIG. 7 shows diagrammatic representations of the transfer function of anamplifier configuration in accordance with FIG. 6 with an overtonecrystal.

FIG. 8 shows a schematic circuit diagram of one example of embodiment ofan improved amplifier configuration in an oscillator circuit inaccordance with the invention.

FIG. 9 shows a schematic circuit diagram of one example of embodiment ofa further improved amplifier configuration in an oscillator circuit inaccordance with the invention.

FIG. 10 shows an example of embodiment of a bandpass filterconfiguration in an oscillator circuit in accordance with the inventionwith a cascade connection of three bandpass stages.

FIG. 11 shows an example of embodiment of a bandpass stage from theexample of embodiment of the bandpass filter configuration in accordancewith FIG. 10.

FIG. 12 shows diagrammatic representations as examples of a transferfunction of an amplifier configuration, in particular in accordance withFIG. 8 or 9, with an overtone crystal and a bandpass filterconfiguration, in particular in accordance with FIG. 10 or 11, and showsan overall transfer function of an example of embodiment of anoscillator circuit formed by it on the occurrence of feedback from thebandpass filter configuration to the amplifier configuration.

FIG. 13 shows diagrammatic representations as examples of an overalltransfer function of an example of embodiment of an oscillator circuitin accordance with the invention as shown in FIG. 3, with an overtonecrystal on the occurrence of feedback from the bandpass filterconfiguration to the amplifier configuration in detailed sections of thediagrammatic representations as shown in FIG. 12.

FIG. 14 shows a schematic circuit diagram of one example of embodimentof a simple converter circuit used in an oscillator circuit inaccordance with the invention to convert a differential signal into anasymmetrically operated electromagnetic oscillation.

FIG. 15 shows a schematic circuit diagram of one example of embodimentof an improved converter circuit used in an oscillator circuit inaccordance with the invention to convert a differential signal into anasymmetrically operated electromagnetic oscillation.

Corresponding elements are always provided with the same referencenumbers herein.

In the schematic circuit diagram, in the form of an alternating currentequivalent network diagram, of the Pierce oscillator in accordance withFIG. 1 in the form of a fundamental frequency oscillator with anoscillator crystal, the oscillator crystal is labeled with the referencenumber 1, and is connected, with each of its two terminals, to an input2 and an output 3 of an inverting amplifier 4. Switched in parallel withthe oscillator crystal 1 is a load resistor 5. The input 2 and theoutput 3 of the amplifier 4 are routed via two capacitors, 6 and 7respectively, to a ground terminal 8.

In very general terms, an oscillatory system is characterized in that ithas a feedback loop, the transfer function of which fulfills the“oscillation condition” when the loop is open, i.e. the sum of thetransfer function is greater than or equal to 1 and its phase responseequals a multiple of 360°. An undesirable resonant frequency in thisoscillatory system can be suppressed in that, at this frequency, the sumof the transfer function is smaller than 1 and/or its phase responsedeviates from a multiple of 360°.

FIG. 2 shows a modification of the Pierce oscillator in accordance withFIG. 1 for operation on a harmonic of the oscillator crystal 1. To thisend, an LC series resonant circuit, formed from a series circuit of aresonant-circuit capacitor 9 and a resonant-circuit inductor 10, isexternally switched in parallel with the oscillator crystal. The seriesresonant circuit 9, 10 is tuned to the fundamental oscillation of theoscillator crystal. As a result, this fundamental oscillation isshort-circuited between the input 2 and the output 3 of the amplifier 4.Consequently, the sum of the transfer function is less than 1 at thefrequency of this fundamental oscillation, and therefore the oscillationcondition is not fulfilled.

As already stated above, strictly speaking, every unwanted resonantfrequency of the oscillator crystal, but at least every one wherein thefrequency is lower than the frequency of the desired harmonic of theoscillator crystal, and is therefore lower than the desired frequency ofthe oscillator, has to be attenuated by a separate LC series resonantcircuit, i.e. during operation at, for example, the fifth harmonic ofthe oscillator crystal, the fundamental oscillation and the thirdharmonic each have to be attenuated by an appropriately tuned LC seriesresonant circuit. Therefore, only harmonic oscillators with suppressionof the fundamental oscillation, which are operated on the thirdharmonic, are commonly encountered in practice, since the oscillatorscircuits would otherwise be too complex.

FIG. 3 shows, in a schematic form, a circuit diagram of one example ofembodiment of an oscillator circuit in accordance with the invention.This comprises an amplifier configuration 11 with pairs of symmetricalinputs 12, 13 and outputs 14, 15, designated differential inputs andoutputs. Connected to the pair of symmetrical outputs 14, 15 with itsterminals 16, 17 is an oscillator crystal 1. A bandpass filterconfiguration 18 is connected, with a pair of symmetrical inputs 19, 20,to the terminals 16 and 17 respectively of the oscillator crystal 1 andto the pair of symmetrical outputs 14, 15 of the amplifier configuration11. The bandpass filter configuration 18 is back-coupled, with a pair ofsymmetrical outputs 21, 22, to the pair of symmetrical inputs 12, 13 ofthe amplifier configuration 11, and the feedback loop of the oscillatorysystem is thereby closed. As a result of its design with differentialinputs and outputs, the oscillator circuit is formed from the amplifierconfiguration 11, the oscillator crystal 1 and the bandpass filterconfiguration 18 for processing electromagnetic oscillations (known asdifferential signals), operated at least virtually symmetricallyrelative to a first reference potential. The first reference potentialhereby corresponds to the direct-current operating point of theamplifier configuration 11 and, preferably, also to that of the bandpassfilter configuration 18, and thereby that of the oscillator circuit as awhole.

In the oscillator circuit in accordance with FIG. 3, the amplifierconfiguration 11 is equipped with a transfer function, the frequencyresponse of which depends on the properties of the connected oscillatorcrystal 1. The amplitude-frequency characteristic of the transferfunction of the amplifier configuration 11 shows maxima in the range ofthe resonance frequencies of the oscillator crystal 1, since itsimpedance shows maxima here. By the dimensioning of theamplitude-frequency characteristic and/or of the phase-frequencycharacteristic of the bandpass filter configuration 18 as a function ofthe amplitude-frequency characteristic and the phase-frequencycharacteristic of the amplifier configuration 11 and of the oscillatorcrystal 1, it is achieved that the oscillation condition is fulfilled inthe oscillator circuit for exclusively a selected harmonic of theoscillator crystal 1, and the high-frequency electromagnetic oscillationformed as a result of this selected harmonic of the oscillator crystal 1is available at the outputs 21, 22 of the bandpass filter configuration18. To put it another way, the bandpass filter configuration 18 is tunedto the selected harmonic of the oscillator crystal 1 and the gain factor(i.e. the amplitude-frequency characteristic) of the amplifierconfiguration 11 is dimensioned to be just large enough that, with anopen loop, the sum of the transfer function of the amplifierconfiguration 11, the oscillator crystal 1 and the bandpass filterconfiguration 18 is greater than or equal to 1 only at the selectedharmonic of the oscillator crystal. Moreover, at this selected harmonicof the oscillator crystal 1, the phase condition must be fulfilled. Theoscillator circuit then oscillates precisely at the selected harmonic ofthe oscillator crystal 1.

In FIG. 3, an output signal of the oscillator circuit is tapped off fromthe outputs 21, 22 of the bandpass filter configuration 18 via aconverter circuit 23, which serves for conversion of the differentialsignal emitted from these differential outputs 21, 22 into anelectromagnetic oscillation operated asymmetrically relative to thedirect-current operating point of the bandpass filter configuration 18.To this end, the pair of differential outputs 21, 22 of the bandpassfilter configuration 18 is coupled with a pair of differential inputs,24 and 25 respectively, of the converter circuit 23. The asymmetricallyoperated electromagnetic oscillation is emitted at one output 26 of theconverter circuit 23. It may preferably take the form of a square-wavesignal.

In FIG. 3, the arrows 27 indicate the direction of the signal flow inthe oscillator circuit shown.

For a more detailed explanation of the function of the amplifierconfiguration 11, let us briefly examine the equivalent network diagramof an oscillator crystal 1, as shown schematically in FIG. 4. Accordingto this, the oscillator crystal represents an electrical two-terminalnetwork, which comprises, in a manner that is known per se, a parallelcircuit of a series resonant circuit comprising a capacitor 28, aninductor 29 and an ohmic resistor 30 on the one hand, and a terminalcapacitor 31 on the other. The capacitor 28 and the inductor 29 arehereby determined by the mechanical properties of the oscillatorcrystal, the ohmic resistor is determined by its attenuation, and theterminal capacitor 31 by the size of the electrodes and leads. At theresonance of the series resonant circuit comprising the capacitor 28,the inductor 29 and the ohmic resistor 30, the oscillator crystal 1,measured between its terminals 16 and 17, possesses a very lowimpedance; at the so-called parallel resonance, lying at a slightlyhigher frequency, which is formed together with the terminal capacitor31, the impedance rises considerably.

In the case of an oscillator crystal 1, which, in FIG. 5, takes the formof an overtone crystal, which possesses multiple resonance frequencies,this change in the sum of the impedance of the oscillator crystal 1 isalso observable with every crystal overtone oscillation. FIG. 5 shows,in simplified form, an equivalent network diagram of an overtone crystalwith supplementary elements for the third and the fifth harmonic inaddition to the fundamental oscillation. In FIG. 5, a series circuitcomprising a capacitor 32, an inductor 33 and an ohmic resistor 34 formsa series resonant circuit to represent the series resonance at the thirdharmonic; a series circuit comprising a capacitor 35, an inductor 36 andan ohmic resistor 37 forms a series resonant circuit to represent theseries resonance at the fifth harmonic, etc.

This response of the oscillator crystal 1 is used in the amplifierconfiguration 11 described below in order to obtain an explicitlypronounced peak of the sum of the gain at every parallel resonance ofthe oscillator crystal 1. The schematic circuit diagram of one exampleof embodiment of an amplifier configuration 11 of this kind is shown inFIG. 6. This amplifier configuration 11 is equipped with a differentialinput stage, which comprises two field effect transistors 38 and 39,connected together at their source terminals 40 and 41 respectively, andconnected to a first terminal 43 of a constant current source 42. Asecond terminal 44 of the constant current source 42 is connected to asupply-voltage terminal 45, at which a supply voltage, preferablyforming a third reference potential, is delivered.

Gate terminals of the field effect transistors 38 and 39 form the firstand second symmetrical (differential) inputs, 12 and 13 respectively, ofthe amplifier configuration 11. Drain terminals of the field effecttransistors 38 and 39 form the first and second symmetrical(differential) inputs, 14 and 15 respectively, of the amplifierconfiguration 11, to connect the oscillator crystal 1, shown with brokenlines, via its terminals, 16 and 17 respectively. These drain terminals,i.e. the outputs 14 and 15 respectively of the amplifier configuration11, are further coupled, in each case via a load path, each of whichcomprises a field effect transistor, designated an output-loadtransistor 46 and 47, with a terminal carrying a second referencepotential. The ground potential at ground terminal 8 is selected herebyas the second reference potential. A control voltage for setting loadcurrents flowing in the output-load transistors 46 and 47 is supplied,via a common control voltage terminal 48, to gate terminals of theoutput-load transistors 46 and 47.

In FIGS. 4 to 6, the arrows 27 again indicate the direction of thesignal flow in the circuits shown.

The loading of the field effect transistors 38 and 39 of thedifferential input stage of the amplifier configuration 11 is formed bythe output load transistors 46 and 47 and the oscillator crystal 1. Forlow frequencies, this circuit possesses a high gain, determined by thetransistor geometry, which steadily decreases from a cut-off frequencydetermined by the ohmic resistors of the output load transistors 46 and47 and the terminal capacitor 31 of the oscillator crystal 1.

At each series resonance of the oscillator crystal 1, i.e. at everyseries resonance of one of the series resonant circuits for thefundamental oscillation or one of the harmonics in the equivalentnetwork diagram as shown in FIG. 5, the gain of the combinationcomprising the amplifier configuration 11 and the oscillator crystal 1declines sharply as a result of the breaking down of the sum of theimpedance of the oscillator crystal 1 and then rises sharply at the highimpedance of the following parallel resonance, which is formed togetherwith the terminal capacitor 31. In the range of the parallel resonances,the terminal capacitor 31 hereby becomes ineffective, since it is partof the parallel resonant circuit formed by the oscillator crystal 1. Thelow-pass response formed from the terminal capacitor 31 of theoscillator crystal 1 and the ohmic resistors of the output loadtransistors 46 and 47 is overridden in the range of each parallelresonance.

FIG. 7 shows diagrammatic representations of the transfer function ofthe amplifier configuration 11 as shown in FIG. 6 with an oscillatorcrystal 1 in the form of an overtone crystal. (This diagrammaticrepresentation is referred to as “FIG. 8” in the heading for thepart-diagrams a) to c) contained therein).

In the upper half of part-diagram a) in FIG. 7 is an example of aphase-frequency characteristic of the amplifier configuration 11together with the oscillator crystal 1, which applies to an oscillatorcrystal with resonance frequencies lying at 16 MHz for the fundamentaloscillation and at 48 MHz for the third harmonic. The phase (Phase) isplotted in degrees (deg) over the logarithmic frequency scale (freq) inHertz (Hz) shown in the lower half of part-diagram a) in FIG. 7. Thelower half of part-diagram a) in FIG. 7 shows an example of acorresponding amplitude-frequency characteristic of the amplifierconfiguration 11 together with the oscillator crystal 1, in which thegain (Gain) is plotted in dBV over the logarithmic frequency scale(freq) in Hertz (Hz).

In part-diagram b) of FIG. 7, a detail at 48 MHz is shown of thecharacteristics in part-diagram a) for the range around the thirdharmonic of the oscillator crystal 1 shown by way of example. The detailfrom the amplitude-frequency characteristic (Gain) is shown hereby inthe upper half of part-diagram b) and the detail from thephase-frequency characteristic (Phase) in the lower half of part-diagramb).

In part-diagram c) of FIG. 7, a detail at 16 MHz is shown of thecharacteristics in part-diagram a) for the range around the fundamentaloscillation of the oscillator crystal 1 shown by way of example. Thedetail from the amplitude-frequency characteristic (Gain) is shownhereby in the upper half of part-diagram c) and the detail from thephase-frequency characteristic (Phase) in the lower half of part-diagramc).

It can be seen from these diagrams that the low-pass response describedappears outside the resonant ranges, which is also reflected in thephase response of the circuit. The phase lies outside the resonancepoints of the oscillator crystal 1 at −90°, rises to 0° at the seriesresonance and rises further up to a maximum of +90°, which, however,could be reached only theoretically with an infinitely high quality ofthe oscillator crystal 1, i.e. if the ohmic resistors 30, 34, 37 in theequivalent network diagram of the oscillator crystal 1 as shown in FIG.4 or 5 become zero. This also means that a higher quality of theoscillator crystal 1 leads, within certain limits, to a higher gain.From this maximum above the series resonance, the value of the phaseinitially drops back to 0° at the frequency of the parallel resonanceand subsequently drops further to the value of −90°, which is caused bythe described low-pass response.

Of significance are the zero transitions of the phase-frequencycharacteristic of the interconnection comprising the amplifierconfiguration 11 and oscillator crystal 1, since one of the twonecessary part-conditions of the oscillation condition is fulfilledhere. In the case of a zero transition of the phase-frequencycharacteristic at a series resonance, an especially low gain of saidinterconnection is produced, and, with a zero transition of thephase-frequency characteristic at a parallel resonance, an especiallyhigh gain. As can be seen from the behavior of the amplitude-frequencycharacteristic (Gain) shown in FIG. 7, part-diagrams a) and b), theoscillation condition would be fulfilled with direct back-coupling ofthe signal at the outputs 14, 15 of the amplifier configuration 11 toits inputs 12, 13, both at the fundamental oscillation of the oscillatorcrystal 1 and at its third harmonic. The frequencies for which thisapplies are marked in part-diagrams b) and c) with markers M2 and M3respectively.

FIG. 8 shows a schematic circuit diagram of one example of embodiment ofan amplifier configuration 49, improved relative to the circuit diagramshown in FIG. 6, for use in an oscillator circuit in accordance with theinvention. It shows an addition to the schematic circuit diagram of theamplifier configuration 11 as shown in FIG. 6, comprising acontrol-voltage generation stage 50, an operating-point regulating stage51 and an offset compensation device 52. In the improved amplifierconfiguration 49 as shown in FIG. 8, the elements known from FIG. 6 areagain provided with the same reference numbers.

The control-voltage generation stage 50 in the improved amplifierconfiguration 49 serves to generate a control voltage, which issupplied, via the common control-voltage terminal 48, to the gateterminals of the output load transistors 46 and 47 for setting loadcurrents flowing in the output load transistors 46 and 47. To this end,the control-voltage generation stage 50 comprises a series circuitcomprising a constant current source 54 and a field effect transistor55, bridged between its drain and gate terminals. The source terminal ofthis field effect transistor 55, bridged between its drain and gateterminals, is connected via the drain-source path of a further fieldeffect transistor 56, to the ground terminal 8. A smoothing capacitor 57is inserted between the gate terminal of the field effect transistor 55,bridged between its drain and gate terminals, and the ground terminal 8.In addition, the further field effect transistor 56 of thecontrol-voltage generation stage 50 is connected, with its gateterminal, to the drain terminal of the field effect transistor 55,bridged between its drain and gate terminals. A terminal 53 of theconstant current source 54, facing away from the field effecttransistors 55, 56, is connected to the supply-voltage terminal 45.

In the example of embodiment shown in FIG. 8, the further field effecttransistor 56 of the control-voltage generation stage 50 issimultaneously a component of the operating-point regulating stage 51.This further comprises a first field effect transistor 58, thedrain-source path of which is series-connected in the first load pathwith the output load transistor 46 located there, and a second fieldeffect transistor 59, the drain-source path of which is series-connectedin the second load path with the output load transistor 47 locatedthere. A gate terminal of the first field effect transistor 58 of theoperating-point regulating stage 51 is connected to the firstdifferential output 14 of the amplifier configuration 49. A gateterminal of the second field effect transistor 59 of the operating-pointregulating stage 51 is connected to the second differential output 15 ofthe amplifier configuration 49. The first and second field effecttransistors 58, 59 of the operating-point regulating stage 51 areconnected, with their source terminals, to the ground terminal 8, whichcarries the ground potential as the second reference potential. Theoperating-point regulating stage 51 actuates a regulation of thedirect-current operating point of the voltage at the differentialoutputs 14, 15 of the amplifier configuration 49.

In the example of embodiment shown in FIG. 8, the offset compensationdevice 52 comprises a first high-pass circuit comprising an ohmicresistor 60 and a capacitor 61. This first high-pass circuit 60, 61 isinserted between the first differential input 12 of the amplifierconfiguration 49, the gate terminal of the first field effect transistor38 of the differential amplifier circuit comprising the amplifierconfiguration 49, which is coupled with the first differential input 12(and is also designated the differential input stage of the amplifierconfiguration 49), and the differential output 14 formed by the drainterminal of this first field effect transistor 38. The offsetcompensation device 52 further comprises a second high-pass circuitcomprising an ohmic resistor 62 and a capacitor 63. This secondhigh-pass circuit 62, 63 is inserted between the second differentialinput 13 of the amplifier configuration 49, the gate terminal of thesecond field effect transistor 39 of the differential input stage of theamplifier configuration 49, which is coupled with the seconddifferential input 13, and the differential output 15 formed by thedrain terminal of this second field effect transistor 39. The limitingfrequencies of the first high-pass circuit 60, 61 and of the secondhigh-pass circuit 62, 63 are small compared with the frequency operatingrange of the oscillator circuit, and therefore do not contribute to aphase shift in the environment of the frequency of the selected harmonicof the oscillator crystal 1.

By virtue of the at least theoretically complete symmetry of thedifferential circuit configuration of the oscillator circuit, a build-upoccurs only as a result of thermal noise or asymmetrical interferenceintroduced externally at the terminals 16, 17 of the oscillator crystal1. A significant reduction in the build-up duration can be achieved bymeans of an expansion of the amplifier configuration 49 used in theoscillator circuit in accordance with the invention, as shown in FIG. 9.

FIG. 9 shows a schematic circuit diagram of one example of embodiment ofan amplifier configuration 64, improved relative to the circuit diagramshown in FIG. 8, for use in an oscillator circuit in accordance with theinvention. It shows an addition to the schematic circuit diagram of theamplifier configuration 49 as shown in FIG. 8, comprising an auxiliarystarting circuit 65. In the improved amplifier configuration 64 as shownin FIG. 9, the elements already described with reference to FIG. 8 areprovided with the same reference numbers.

In accordance with the example of embodiment in accordance with FIG. 9,the auxiliary starting circuit 65 comprises a first field effecttransistor 66, a second field effect transistor 67, a start-signal input68 and a delay stage 69. The first field effect transistor 66 of theauxiliary starting circuit 65 is disposed between the gate terminal ofthe first field effect transistor 38 of the differential input stage ofthe amplifier configuration 64 and a terminal carrying a third referencepotential. This terminal carrying the third reference potential isformed in FIG. 9 by the supply-voltage terminal 45 carrying the supplyvoltage. The second field effect transistor 67 of the auxiliary startingcircuit 65 is disposed between the gate terminal of the second fieldeffect transistor 39 of the differential input stage of the amplifierconfiguration 64 and the supply-voltage terminal 45. The start-signalinput 68 is coupled directly with a gate terminal of the first fieldeffect transistor 66 of the auxiliary starting circuit 65, and, via thedelay stage 69, with a gate terminal of the second field effecttransistor 67 of the auxiliary starting circuit 65.

When the oscillator circuit is put into operation, an at least largelypulse-shaped or step-shaped start signal is applied to the start-signalinput 68 from outside. This start signal is supplied directly to thegate terminal of the first field effect transistor 66 of the auxiliarystarting circuit 65, and, with a time delay, to the gate terminal of thesecond field effect transistor 67 of the auxiliary starting circuit 65.As a result, during a predetermined period when the oscillator circuitis put into operation, a differential voltage is supplied to the gateterminals of the field effect transistors 38, 39 of the differentialinput stage of the amplifier configuration 64, as a result of which atime-limited interference is deliberately introduced and the symmetrypredetermined by the differential oscillator circuit is thus brieflyoverridden.

FIG. 10 shows an example of embodiment of a bandpass filterconfiguration 18 in an oscillator circuit in accordance with theinvention with a cascade connection of three bandpass stages 70, 71 and72, which are disposed between the symmetrical inputs 19, 20 and thesymmetrical outputs 21, 22 of the bandpass filter configuration 18. Thepurpose of the bandpass filter configuration 18 is to select only thedesired resonant frequency from all the resonance frequencies of theoscillator crystal 1 for which the oscillation condition is fulfilled inthe interconnection of the oscillator crystal 1 with the amplifierconfiguration 11, 49 and 64, and to suppress all unwanted resonancefrequencies. Through the dimensioning of the amplitude-frequencycharacteristic and/or the phase-frequency characteristic of the bandpassfilter configuration 18 as a function of the amplitude-frequencycharacteristic and the phase-frequency characteristic of the amplifierconfiguration 11, 49 and 64, and of the oscillator crystal 1, theoscillation condition for the oscillator circuit as a whole, i.e. thephase and/or gain condition for an oscillation, is to be fulfilledthereby exclusively for a selected harmonic of the oscillator crystal,and its fulfillment is to be prevented for the unwanted resonancefrequencies. The harmonic of the oscillator crystal 1 selected in thismanner forms a high-frequency electromagnetic oscillation, which isavailable at the output of the bandpass filter configuration 18.

The three-stage design of the bandpass filter configuration 18 as shownin FIG. 10 enables the individual bandpass stages 70, 71 and 72 to bedesigned with lower quality than if the bandpass filter configuration 18were designed with one single bandpass stage. It can thereby be achievedthat the power consumption of all three bandpass stages 70, 71 and 72together, and thereby of the bandpass filter configuration 18 as awhole, can be kept lower than in the case of a design of the bandpassfilter configuration 18 with one single bandpass stage of high quality.With this design of the bandpass stages 70, 71 and 72, however, thefulfillment of the oscillation condition will be prevented principallyby the phase-frequency characteristic of the bandpass filterconfiguration 18; i.e. the phase condition for an oscillation of theoscillator circuit is fulfilled only in the range of the selectedharmonic of the oscillator crystal 1, and not at the remaining resonancefrequencies of the amplifier configuration 11, 49 and 64 and of theoscillator crystal 1. On the other hand, the amplitude-frequencycharacteristic of the bandpass filter configuration 18 designed in thisway only exhibits, over the frequency, a change so small that the gaincondition for an oscillation of the oscillator circuit can still befulfilled in the range of the resonance frequencies of the amplifierconfiguration 11, 49 and 64 and of the oscillator crystal 1 that areadjacent to the selected harmonic of the oscillator crystal 1. So theamplitude-frequency characteristic of the bandpass filter configuration18 designed in this way would not suffice per se for a frequencyselection.

In the bandpass filter configuration 18 in accordance with FIG. 10, thefirst bandpass stage 70 is equipped with a first symmetrical input 73, asecond symmetrical input 74, a first symmetrical output 75 and a secondsymmetrical output 76. The second bandpass stage 71 is equipped with afirst symmetrical input 77, a second symmetrical input 78, a firstsymmetrical output 79 and a second symmetrical output 80. The thirdbandpass stage 72 is equipped with a first symmetrical input 81, asecond symmetrical input 82, a first symmetrical output 83 and a secondsymmetrical output 84.

The first differential (or symmetrical) input 73 of the first bandpassstage 70 forms the first symmetrical input 19 of the bandpass filterconfiguration 18. The second differential (or symmetrical) input 74 ofthe first bandpass stage 70 forms the second symmetrical input 20 of thebandpass filter configuration 18. The first symmetrical output 75 of thefirst bandpass stage 70 is connected to the first symmetrical input 77of the second bandpass stage 71 in a first junction point 85. The secondsymmetrical output 76 of the first bandpass stage 70 is connected to thesecond symmetrical input 78 of the second bandpass stage 71 in a secondjunction point 86. The first symmetrical output 79 of the secondbandpass stage 71 is connected to the first symmetrical input 81 of thethird bandpass stage 72 in a third junction point 87. The secondsymmetrical output 80 of the second bandpass stage 71 is connected tothe second symmetrical input 82 of the third bandpass stage 72 in afourth junction point 88. The first differential (or symmetrical) output83 of the third bandpass stage 72 forms the first symmetrical output 21of the bandpass filter configuration 18. The second differential (orsymmetrical) output 84 of the third bandpass stage 72 forms the secondsymmetrical output 22 of the bandpass filter configuration 18.

Arrows 27 again indicate the direction of the signal flow in thecircuits shown.

FIG. 11 shows the first bandpass stage 70 as an example of embodiment ofa bandpass stage from the example of embodiment of the bandpass filterconfiguration 18 in accordance with FIG. 10. This bandpass stage 70comprises a differential amplifier circuit comprising a first fieldeffect transistor 89 and a second field effect transistor 90, which arecoupled together by linking their source terminals to one another andfurther coupled at this link to a first terminal 91 of a first constantcurrent source 92. A second terminal 93 of the first constant currentsource 92 is linked to the supply-voltage terminal 45. A drain terminalof the first field effect transistor 89 of the first bandpass stage 70forms the second output 76 of the first bandpass stage 70. A drainterminal of the second field effect transistor 90 of the first bandpassstage 70 forms the first output 75 of the first bandpass stage 70.

In the first bandpass stage 70, the first differential input 73 iscoupled, via a first high-pass circuit, to a gate terminal of the firstfield effect transistor 89. This first high-pass circuit comprises afirst high-pass capacitor 94, via which the first differential input 73is coupled with the gate terminal of the first field effect transistor89, and a first high-pass resistor 95, which is connected with a firstterminal 96 to the gate terminal of the first field effect transistor89. The second differential input 74 is further coupled, via a secondhigh-pass circuit, to a gate terminal of the second field effecttransistor 90. This second high-pass circuit comprises a secondhigh-pass capacitor 97, via which the second differential input 74 iscoupled with the gate terminal of the second field effect transistor 90,and a second high-pass resistor 98, which is connected with a firstterminal 99 to the gate terminal of the first field effect transistor90. The first high-pass resistor 95 and the second high-pass resistor 98are connected to one another at their second terminals 100 and 101respectively, and to an output terminal 102 of a direct-bias-voltagegeneration stage 103. The direct-bias-voltage generation stage 103 ofthe first bandpass stage 70 comprises a second constant current source104, connected in series with a third field effect transistor 105, whichis short-circuited between its gate terminal and its drain terminal,wherein this series circuit is disposed between the supply-voltageterminal 45 and the ground terminal 8. The connection of the gateterminal and the drain terminal of the third field effect transistor 105hereby forms the output terminal 102 of the direct-bias-voltagegeneration stage 103 in order to supply a direct bias voltage for thehigh-pass circuits.

In the first bandpass stage 70 as shown in FIG. 11, the drain terminalof the first field effect transistor 89, which forms the second output76, is further connected, via a first low-pass circuit, to the groundterminal 8, which forms a terminal carrying a fifth reference potential(here: ground potential). The drain terminal of the second field effecttransistor 90, which forms the first output 75 of the first bandpassstage 70, is connected, via a second low-pass circuit, to the groundterminal 8. The first low-pass circuit comprises a parallel circuitcomprising a first low-pass capacitor 106 and a first low-pass resistor107, and the second low-pass circuit comprises a parallel circuitcomprising a second low-pass capacitor 108 and a second low-passresistor 109. The low-pass circuits form the output loads for thedifferential amplifier circuit comprising the first field effecttransistor 89 and the second field effect transistor 90 of the bandpassstage 70.

The low-pass capacitors 106, 108 do not necessarily have to be presentas explicit components in the first bandpass stage 70—and also theremaining bandpass stages—but may also take the form of parasiticcapacitances of the low-pass resistors 107, 109, or input impedances ofdownstream circuit stages connected to the outputs 75, 76 of the firstbandpass stage 70—e.g. the second bandpass stage 71 in this example.

Owing to the fact that the high-pass circuits and low-pass circuits takethe form of RC networks, they can readily be combined with the remainingsemiconductor elements of the oscillator circuit on a semiconductor basein integrated semiconductor technology.

FIG. 12 shows diagrammatic representations as examples of a transferfunction of an amplifier configuration 49 and 64, in particular inaccordance with FIG. 8 or 9, with an oscillator crystal 1 in the form ofan overtone crystal, and a bandpass filter configuration 18, inparticular in accordance with FIG. 10 or 11, and shows an overalltransfer function of an example of embodiment of an oscillator circuitformed by it on the occurrence of feedback from the bandpass filterconfiguration 18 to the amplifier configuration 49 and 64. (Thisdiagrammatic representation is designated “FIG. 12” in the heading tothe part-diagrams a) to c) contained therein).

In the upper half of part-diagram a) in FIG. 12 is an example of aphase-frequency characteristic of the amplifier configuration 49 and 64together with the oscillator crystal 1, which applies to an oscillatorcrystal 1 with resonance frequencies lying at 16 MHz for the fundamentaloscillation and at 48 MHz for the third harmonic. The phase (Phase) isplotted in degrees (deg) over the logarithmic frequency scale (freq) inHertz (Hz) shown in the lower half of part-diagram a) in FIG. 12. Thelower half of part-diagram a) in FIG. 12 shows an example of acorresponding amplitude-frequency characteristic of the amplifierconfiguration 49 and 64 together with the oscillator crystal 1, in whichthe gain (Gain) is plotted in dBV over the logarithmic frequency scale(freq) in Hertz (Hz). Clearly recognizable, in particular in theamplitude-frequency characteristic in the lower half of part-diagram a),is the high-pass characteristic of the offset compensation device 52 inthe amplifier configuration 49 and 64.

In the upper half of part-diagram b) in FIG. 12 is an example of aphase-frequency characteristic of the bandpass filter configuration 18,which is designed for an oscillator crystal 1 dimensioned as indicatedin part-diagram a). Plotted here again is the phase (Phase Bandpass) indegrees (deg) over the logarithmic frequency scale (freq) in Hertz (Hz)shown in the lower half of part-diagram b) in FIG. 12. The lower half ofpart-diagram b) in FIG. 12 shows an example of a correspondingamplitude-frequency characteristic of the bandpass filter configuration18, in which the gain (Gain Bandpass) is plotted in dBV over thelogarithmic frequency scale (freq) in Hertz (Hz). It is clearlyrecognizable in the amplitude-frequency characteristic in the lower halfof part-diagram b), that the attenuation of the amplifier configuration49 and 64 by the bandpass filter configuration 18 is inadequate, eitherfor the fundamental oscillation of the oscillator crystal 1 or for itsfifth harmonic, to prevent the fulfillment of the gain condition as partof the oscillation condition. Conversely, the phase response, i.e. thephase-frequency characteristic, of the bandpass filter configuration 18shows the property that is both desired and required for prevention ofthe fulfillment of the phase condition as part of the oscillationcondition, in that, at the frequency of the fundamental oscillation ofthe oscillator crystal 1, the phase is considerably greater than 90°, atthe frequency of the third harmonic of the oscillator crystal 1 it isaround 0°, and at the frequency of the fifth harmonic of the oscillatorcrystal 1, it is sufficiently close to −90°. To make this clearer, thefrequencies to which this applies are marked, in both halves ofpart-diagram b), with the markers M4 for the third harmonic, M5 for thefundamental oscillation and M6 for the fifth harmonic.

Part-diagram c) in FIG. 12 shows, for the above-explained dimensioningexamples, the phase-frequency characteristic (Phase) in the upper halfand, in the lower half, the corresponding amplitude-frequencycharacteristic (Gain) of the amplifier configuration 49 and 64 togetherwith the oscillator crystal 1 and the bandpass filter configuration 18with an open feedback loop, again plotted in degrees (deg) and in dBVover the logarithmic frequency scale (freq) in Hertz (Hz) plotted in thelower half of part-diagram c) in FIG. 12.

FIG. 13 shows diagrammatic representations of an overall transferfunction of the above-explained dimensioning examples of the oscillatorcircuit in accordance with the invention as shown in FIG. 3, with anoscillator crystal 1 in the form of an overtone crystal on theoccurrence of feedback from the bandpass filter configuration 18 to theamplifier configuration 49 and 64 in detailed sections of thediagrammatic representations as shown in FIG. 12. (This diagrammaticrepresentation is designated “FIG. 13” in the heading to thepart-diagrams a) to c) contained therein). In part-diagram a) of FIG.13, a detail at 16 MHz is shown of the overall transfer function frompart-diagram c) in FIG. 12 for the range around the fundamentaloscillation of the oscillator crystal 1 shown by way of example.Part-diagram b) of FIG. 13 shows a detail at 48 MHz of the overalltransfer function in part-diagram c) of FIG. 12 for the range around thethird harmonic of the oscillator crystal 1 shown by way of example, andpart-diagram c) of FIG. 13 shows a detail at 80 MHz of the overalltransfer function from part-diagram c) in FIG. 12 for the range aroundthe fifth harmonic of this oscillator crystal 1. The detail from theamplitude-frequency characteristic (Gain) is shown hereby in the upperhalf of part-diagrams a), b), c) and the detail from the phase-frequencycharacteristic (Phase) in the lower half of part-diagrams a), b) c). Thegain (Gain) is again plotted in dBV and the phase (Phase) in degrees(deg) over the logarithmic frequency scales (freq) in Hertz (Hz) in thelower halves of part-diagrams a), b), c) in FIG. 12.

It is apparent, in particular from the diagrammatic details shown inFIG. 13, that, by virtue of the connection of the bandpass filterconfiguration 18 downstream of the amplifier configuration 49 and 64,both the gain condition and the phase condition for an oscillation arefulfilled only at the desired third harmonic, which is indicated inpart-diagram b) of FIG. 13 with marker M1, and not at the fundamentaloscillation in accordance with part-diagram a) of FIG. 13 or at thefifth harmonic in accordance with part-diagram c) of FIG. 13.

FIG. 14 shows a schematic circuit diagram of one example of embodimentof a simple converter circuit 23 used in an oscillator circuit inaccordance with the invention to convert a differential signal into anelectromagnetic oscillation that is operated asymmetrically relative tothe direct-current operating point of the bandpass filter configuration18, and thereby preferably relative to that of the oscillator circuit asa whole.

To this end, the converter circuit 23 in accordance with FIG. 14contains an input stage, in the form of a differential amplifier withfield effect transistors 110 and 111 coupled at their source terminals,to which the differential signal to be converted is supplied from thesymmetrical outputs 21, 22 of the bandpass filter configuration 18 viagate terminals f the field effect transistors 110 and 111. The gateterminal of the first field effect transistor 110 hereby forms the firstdifferential input 24 of the converter circuit 23, and the gate terminalof the second field effect transistor 111 forms the second differentialinput 25 of the converter circuit 23. A first constant current source112 of the converter circuit 23 is connected, with its first terminal113, to the junction point of the source terminals of the field effecttransistors 110 and 111, and, with its second terminal 114, to thesupply-voltage terminal 45. A drain terminal of the second field effecttransistor 111 forms a first output terminal 116 of the input stage ofthe converter circuit 23 to supply a first differential output signal ofthe input stage of the converter circuit 23. A drain terminal of thefirst field effect transistor 110 forms a second output terminal 115 ofthe input stage of the converter circuit 23 to supply a seconddifferential output signal of the input stage of the converter circuit23.

The converter circuit 23 further comprises a first current mirror stageto mirror the first differential output signal at the first outputterminal 116 of the input stage of the converter circuit 23 into a firstintermediate signal. This first current mirror stage comprises a firstand a second field effect transistor 117 and 118, which are coupled viatheir gate terminals. The first field effect transistor 117 of the firstcurrent mirror stage hereby forms its input transistor, and isshort-circuited between its drain and gate terminals. The sourceterminals of the field effect transistors 117, 118 are supplied jointlyto the ground terminal 8. A drain terminal of the second field effecttransistor 118 forms an output terminal 119 of the first current mirrorstage 117, 118 of the converter circuit 23, at which the firstintermediate signal is supplied.

The converter circuit 23 further comprises a second current mirror stageto mirror the second differential output signal at the second outputterminal 115 of the input stage of the converter circuit 23 into asecond intermediate signal. This second current mirror stage comprises afirst and a second field effect transistor 120 and 121, which arecoupled via their gate terminals. The first field effect transistor 120of the second current mirror stage hereby forms its input transistor,and is short-circuited between its drain and gate terminals. The sourceterminals of the field effect transistors 120, 121 are supplied jointlyto the ground terminal 8. A drain terminal of the second field effecttransistor 121 forms an output terminal 122 of the second current mirrorstage 120, 121 of the converter circuit 23, at which the secondintermediate signal is supplied.

The converter circuit 23 further comprises a third current mirror stageto mirror the first intermediate signal at the first output terminal 119of the first current mirror stage 117, 118 of the converter circuit 23into a third intermediate signal. This third current mirror stagecomprises a first and a second field effect transistor 123 and 124,which are coupled via their gate terminals. The first field effecttransistor 123 of the third current mirror stage hereby forms its inputtransistor, and is short-circuited between its drain and gate terminals.The source terminals of the field effect transistors 123, 124 of thethird current mirror stage are supplied jointly to the supply-voltageterminal 45. A drain terminal of the second field effect transistor 124forms an output terminal 125 of the third current mirror stage 123, 124of the converter circuit 23, at which the third intermediate signal issupplied.

Finally, the converter circuit 23 comprises a subtraction circuit tosubtract the second intermediate signal from the third intermediatesignal, which takes the form of a current node 126 between the outputterminal 122 of the second current mirror stage 120, 121 and the outputterminal 125 of the third current mirror stage 123, 124 of the convertercircuit 23. This current node 126 is coupled, via an output drivercircuit 127, with the output 26 of the converter circuit 23, to amplifyand supply the electromagnetic oscillation that is operatedasymmetrically relative to the direct-current operating point.

With a sufficiently high gain of the differential input signal suppliedto it, the converter circuit 23 shown in FIG. 14 brings about itsconversion into an at least largely square-wave signal, switchingbetween two voltage potentials determined by the design with fieldeffect transistors, which is also designated a “digital, asymmetricallyoperated signal with CMOS levels”, provided the field effect transistorsused are of the CMOS type.

It transpires, however, that in the case of this circuit, the junctionpoint of the gate terminals of the field effect transistors 123 and 124of the third current mirror stage has only a relatively low voltageswing in operation. This voltage swing is restricted towards highvoltage potentials by the threshold voltage of the first field effecttransistor 123. Towards low voltage potentials, the voltage swing isrestricted by the design of this first field effect transistor 123 andthe highest possible value of the current through the second fieldeffect transistor 118 of the first current mirror stage of the convertercircuit 23. This highest possible value of the current through thesecond field effect transistor 118 of the first current mirror stage ofthe converter circuit 23 arises when the voltage potential at the seconddifferential input 25 of the converter circuit 23 assumes its mostnegative possible value, and simultaneously the voltage potential at thefirst differential input 24 of the converter circuit 23 assumes its mostpositive value.

By virtue of the fact that the described voltage swing at the junctionpoint of the gate terminals of the field effect transistors 123 and 124of the third current mirror stage of the converter circuit 23 is subjectto relatively narrow restriction, the second field effect transistor 124is de-energized only slowly and incompletely at the highest possiblevoltage potential at the junction point of the gate terminals of thefield effect transistors 123 and 124 of the third current mirror stage,so the current forming the second intermediate signal, which dischargesthe current node 126 of the converter circuit 23 when the differencebetween the voltage potential at the second differential input 25 andthe voltage potential at the first differential input 24 of theconverter circuit 23 is tending to positive, operates only with a delay,and not immediately, on a high input impedance of the second fieldeffect transistor 124 of the third current mirror stage of the convertercircuit 23. Correspondingly, this current, which forms the secondintermediate signal, undertakes not only the recharging of the currentnode 126, but also a proportion of this current flows as a cross currentthrough said second field effect transistor 124. As a result, thedischarging of the current node 126 is retarded.

When the difference between the voltage potential at the seconddifferential input 25 and the voltage potential at the firstdifferential input 24 of the converter circuit 23 is tending to becomepositive, the voltage swing at the junction point of the gate terminalsof the field effect transistors 123 and 124 of the third current mirrorstage, which is restricted towards low voltage potentials, leads to thesituation where the second field effect transistor 124 is energized onlywith a delay and not instantaneously, and with the lowest possiblevoltage potential at its gate terminal, so this second field effecttransistor 124 charges the current node 126 only at decelerated speed.

The procedures described lead to the situation where the edge steepnessof the signal at the current node 126, and thereby the edge steepness ofthe electromagnetic oscillation delivered at the output 26 of theconverter circuit 23, which is intended to form an at least largelysquare-wave signal, turns out to be relatively small. It transpires thatthis relatively small edge steepness contributes to the fact that theabove-mentioned interference leads to increased “jitter” of theelectromagnetic oscillation delivered at the output 26 of the convertercircuit 23.

FIG. 15 shows a schematic circuit diagram of one example of embodimentof a converter circuit 128, which is improved relative to the convertercircuit 23 in accordance with FIG. 14 and is used in an oscillatorcircuit in accordance with the invention to convert a differentialsignal into an asymmetrically operated electromagnetic oscillation. Theelements described in FIG. 14 are again provided with the same referencenumbers.

In the improved converter circuit 128, the third current mirror stage123, 124 is coupled with an auxiliary switch-on stage equipped with afirst cascode field effect transistor 129 in the input arm of the thirdcurrent mirror stage 123, 124. To this end, this first cascode fieldeffect transistor 129 is connected, with its drain-source path, inseries with the drain-source path of the first field effect transistor123 of the third current mirror stage 123, 124, wherein a drain terminalof the first field effect transistor 123 is connected to a sourceterminal of the first cascode field effect transistor 129, and a drainterminal of the first cascode field effect transistor 129 is connectedto the output terminal 119 of the first current mirror stage 117, 118 ofthe converter circuit 128. The gate terminal of the first field effecttransistor 123 of the third current mirror stage 123, 124 is nowconnected to the drain terminal of the first cascode field effecttransistor 129.

In addition, in the improved converter circuit 128, the third currentmirror stage 123, 124 is coupled with an auxiliary switch-off stage.This comprises a first cascaded stage with, connected between thesupply-voltage terminal 45 and the ground terminal 8, a series circuitcomprising a first field effect transistor 130, an input transistor 131of a fourth current mirror stage in the form of a field effecttransistor, and a second cascode field effect transistor 132 in theinput arm of the fourth current mirror stage. The first field effecttransistor 130 of the first cascaded stage is inserted into the secondcurrent mirror stage 120, 121 in that its source terminal is connectedto the ground terminal 8, and its gate terminal is connected to the gateterminal of the first field effect transistor 120 of the second currentmirror stage 120, 121 of the converter circuit 128, and, together withthis second current mirror stage 120, 121, is operated through thesecond differential output signal of the input stage 110, 111 of theconverter circuit 128. The first field effect transistor 130 of thefirst cascaded stage hereby delivers, at its drain terminal, a fourthintermediate signal, which is, at least over sections, essentiallyproportional to the second intermediate signal. The second cascode fieldeffect transistor 132 is connected in series, with its drain-sourcepath, to the drain-source path of the input transistor 131 of the fourthcurrent mirror stage, wherein a drain terminal of the input transistor131 of the fourth current mirror stage is connected to a source terminalof the second cascode field effect transistor 132. The gate terminal ofthe input transistor 131 of the fourth current mirror stage is connectedto the drain terminal of the second cascode field effect transistor 132.

The fourth current mirror stage in the auxiliary switch-off stage of theimproved converter circuit 128 is provided to mirror the fourthintermediate signal delivered by the first field effect transistor 130of the first cascaded stage into a fifth intermediate signal and to feedthis into the third current mirror stage 123, 124, and comprises theinput transistor 131, in the form of a field effect transistor, todeliver the fourth intermediate signal, and an output transistor 133, inthe form of a field effect transistor, to deliver the fifth intermediatesignal. The input transistor 131 and the output transistor 133 of thefourth current mirror stage 131, 133 are connected together with theirgate terminals. Furthermore, the input transistor 131 and the outputtransistor 133 of the fourth current mirror stage 131, 133 are connectedat their source terminals to the supply-voltage terminal 45. A drainterminal of the output transistor 133 of the fourth current mirror stage131, 133 is connected to the gate terminals of the third current mirrorstage 123, 124.

Finally, in the improved converter circuit 128, a cascode-bias-voltagegeneration circuit is provided to deliver a common cascode bias voltageto coupled-together gate terminals of the first and second cascode fieldeffect transistors 129 and 132 respectively. This cascode-bias-voltagegeneration circuit comprises a series circuit comprising a first fieldeffect transistor 134, a second field effect transistor 135 and a secondconstant current source 136. This series circuit is disposed between aterminal (here: ground terminal 8) carrying a sixth reference potential(here: ground potential) and a terminal (here: the supply-voltageterminal 45) carrying a seventh reference potential (here: the supplyvoltage). This first field effect transistor 134 is hereby connected,with its drain terminal, to a source terminal of the second field effecttransistor 135. Gate terminals of this first and this second fieldeffect transistor, 134, 135, are connected to each other, to a drainterminal of this second field effect transistor 135, to a first terminalof the second constant current source 136 and to the gate terminals ofthe first and second cascode field effect transistors 129 and 132, inorder to deliver the common cascode bias voltage. A source terminal ofthe first field effect transistor 134 of the cascode-bias-voltagegeneration circuit is connected to the supply-voltage terminal 45, and asecond terminal of the second constant current source 136 is deliveredto the ground terminal 8.

The improved converter circuit 128 in accordance with FIG. 15 reducesthe described interference effects and increases the edge steepness ofthe signal at the current node 126, and thereby the edge steepness ofthe electromagnetic oscillation delivered at the output 26 of theconverter circuit 128, in that the voltage swing and the edge steepnessof the signal at the junction point of the gate terminals of the fieldeffect transistors 123 and 124 of the third current mirror stage areincreased in operation. The first cascode field effect transistor 129 ofthe improved converter circuit 128 increases the load impedance of thecurrent carried by the second field effect transistor 118 of the firstcurrent mirror stage 117, 118 of the converter circuit 128 (i.e. thecurrent of the first intermediate signal), and thereby leads to anincreased voltage swing towards lower voltage potentials, and to anincreased edge steepness of the decaying signal at the junction point ofthe gate terminals of the field effect transistors 123 and 124 of thethird current mirror stage 123, 124, as a result of which the secondfield effect transistor 124 of the third current mirror stage 123, 124of the converter circuit 128 is energized more quickly and with lowerimpedance.

A rapid, steep switch-off of the second field effect transistor 124 ofthe third current mirror stage 123, 124 of the converter circuit 128 isrealized by the output transistor 133 of the fourth current mirror stage131, 133 of the auxiliary switch-off stage and its control signal, alsosteepened via the first cascaded stage 130, 131, 132, at thecoupled-together gate terminals of the transistors 131, 133 of thefourth current mirror stage 131, 133. Through the output transistor 133of the fourth current mirror stage 131, 133, the junction point of thegate terminals of the third current mirror stage 123, 124 is charged upto the positive supply voltage at the supply-voltage terminal 45, andthe second field effect transistor 124 of the third current mirror stage123, 124 is switched to very high resistivity, so that the second fieldeffect transistor 121 of the second current mirror stage 120, 121 candischarge the current node 126 as rapidly as possible. The cascode biasvoltage is set by the first and the second field effect transistor 134,135 respectively, and by a constant current from the secondconstant-current source 136 of the cascode-bias-voltage generationcircuit of the improved converter circuit 128. At its output 26, theimproved converter circuit 128 delivers an extremely good, square-wavesignal, which switches between the supply voltage and ground potentialand which is also designated a “Digital, asymmetrically operated signalwith CMOS levels”.

All the circuit configurations described above can be constructed in a“CMOS process” or a “N-Well/P-Well process”. A complementary structure,exchanging pMOS transistors for nMOS transistors and vice versa, withbalancing of the supply-voltage potentials, is, of course, alsopossible.

LIST OF REFERENCE NUMBERS

1 Crystal oscillator

2 Input of the inverting amplifier 4

3 Output of the inverting amplifier 4

4 Inverting amplifier

5 Load resistor

6 Capacitor between input 2 of the amplifier 4 and ground terminal 8

7 Capacitor between output 3 of the amplifier 4 and ground terminal 8

8 Ground terminal

9 Resonant circuit capacitor (of the LC series resonant circuit)

10 Resonant circuit inductance (of the LC series resonant circuit)

11 Amplifier configuration in accordance with FIG. 6

12 First symmetrical (differential) input of the amplifier configuration11, 49 and 64

13 Second symmetrical (differential) input of the amplifierconfiguration 11, 49 and 64

14 First symmetrical (differential) output of the amplifierconfiguration 11, 49 and 64

15 Second symmetrical (differential) output of the amplifierconfiguration 11, 49 and 64

16 First terminal of the crystal oscillator 1

17 Second terminal of the crystal oscillator 1

18 Bandpass filter configuration 18

19 First symmetrical input of the bandpass filter configuration 18

20 Second symmetrical input of the bandpass filter configuration 18

21 First symmetrical output of the bandpass filter configuration 18

22 Second symmetrical output of the bandpass filter configuration 18

23 Converter circuit

24 First differential input of the converter circuit 23 and 128

25 Second differential input of the converter circuits 23 and 128

26 Output of the converter circuits 23 and 128

27 Arrows to show the direction of the signal flow in the oscillatorcircuit

28 Capacitor in the equivalent network diagram of the crystal oscillator1 (fundamental oscillation)

29 Inductance in the equivalent network diagram of the oscillatorcrystal 1 (fundamental oscillation)

30 Ohmic resistor in the equivalent circuit diagram of the oscillatorcrystal 1 (fundamental oscillation)

31 Terminal capacitor in the equivalent circuit diagram of theoscillator crystal 1

32 Capacitor in the equivalent circuit diagram of the oscillator crystal1 (third harmonic)

33 Inductor in the equivalent circuit diagram of the oscillator crystal1 (third harmonic)

34 Ohmic resistor in the equivalent circuit diagram of the oscillatorcrystal 1 (third harmonic)

35 Capacitor in the equivalent circuit diagram of the oscillator crystal1 (fifth harmonic)

36 Inductor in the equivalent circuit diagram of the oscillator crystal1 (fifth harmonic)

37 Ohmic resistor in the equivalent circuit diagram of the oscillatorcrystal 1 (fifth harmonic)

38 First field effect transistor of the differential input stage of theamplifier configuration 11, 49 and 64

39 Second field effect transistor of the differential input stage of theamplifier configuration 11, 49 and 64

40 Source terminal of the first field effect transistor 38

41 Source terminal of the second field effect transistor 39

42 Constant current source

43 First terminal of the constant current source 42

44 Second terminal of the constant current source 42

45 Supply voltage terminal

46 First output load transistor, connected to the first field effecttransistor 38

47 Second output load transistor, connected to the second field effecttransistor 39

48 Control voltage terminal for the output load transistors 46 and 47

49 Improved amplifier configuration in accordance with FIG. 8

50 Control-voltage generation stage in the improved amplifierconfiguration 49

51 Operating-point regulating stage in the improved amplifierconfiguration 49

52 Offset compensation device in the improved amplifier configuration 49

53 Terminal of the constant current source 54 of the control-voltagegeneration stage 50, connected to the supply-voltage terminal 45

54 Constant current source of the control-voltage generation stage 50

55 Field effect transistor of the control-voltage generation stage 50,bridged between its drain and gate terminals

56 Further field effect transistor of the control-voltage generationstage 50

57 Smoothing capacitor of the control-voltage generation stage 50

58 First field effect transistor of the operating-point regulating stage51

59 Second field effect transistor of the operating-point regulatingstage 51

60 Ohmic resistor of the first high-pass circuit

61 Capacitor of the first high-pass circuit

62 Ohmic resistor of the second high-pass circuit

63 Capacitor of the second high-pass circuit

64 Improved amplifier configuration in accordance with FIG. 9

65 Auxiliary starting circuit of the improved amplifier configuration 64in accordance with FIG. 9

66 First field effect transistor of the auxiliary starting circuit 65

67 Second field effect transistor of the auxiliary starting circuit 65

68 Start-signal input of the auxiliary starting circuit 65

69 Delay stage of the auxiliary starting circuit 65

70 First bandpass stage of the bandpass filter configuration 18 inaccordance with FIG. 10

71 Second bandpass stage of the bandpass filter configuration 18 inaccordance with FIG. 10

72 Third bandpass stage of the bandpass filter configuration 18 inaccordance with FIG. 10

73 First symmetrical input of the first bandpass stage 70

74 Second symmetrical input of the first bandpass stage 70

75 First symmetrical output of the first bandpass stage 70

76 Second symmetrical output of the first bandpass stage 70

77 First symmetrical input of the second bandpass stage 71

78 Second symmetrical input of the second bandpass stage 71

79 First symmetrical output of the second bandpass stage 71

80 Second symmetrical output of the second bandpass stage 71

81 First symmetrical input of the third bandpass stage 72

82 Second symmetrical input of the third bandpass stage 72

83 First symmetrical output of the third bandpass stage 72

84 Second symmetrical output of the third bandpass stage 72

85 First junction point between 75 and 77

86 Second junction point between 76 and 78

87 Third junction point between 79 and 81

88 Fourth junction point between 80 and 82

89 First field effect transistor of the first bandpass stage 70

90 Second field effect transistor of the first bandpass stage 70

91 First terminal of the constant current source 92

92 First constant current source of the first bandpass stage 70

93 Second terminal of the first constant current source 92

94 First high-pass capacitor of the first high-pass circuit of the firstbandpass stage 70

95 First high-pass resistor of the first high-pass circuit of the firstbandpass stage 70

96 First terminal of the first high-pass resistor 95 of the firsthigh-pass circuit (first bandpass stage 70)

97 Second high-pass capacitor of the second high-pass circuit of thefirst bandpass stage 70

98 Second high-pass resistor of the second high-pass circuit of thefirst bandpass stage 70

99 First terminal of the second high-pass resistor 98 of the secondhigh-pass circuit (first bandpass stage 70)

100 Second terminal of the first high-pass resistor 95 of the firsthigh-pass circuit (first bandpass stage 70)

101 Second terminal of the second high-pass resistor 98 of the secondhigh-pass circuit (first bandpass stage 70)

102 Output terminal 102 of the direct-bias-voltage generation stage 103of the first bandpass stage 70

103 Direct-bias-voltage generation stage 103 of the first bandpass stage70

104 Second constant current source 104 of the direct-bias-voltagegeneration stage 103 of the first bandpass stage 70

105 Third field effect transistor 105 of the direct-bias-voltagegeneration stage 103 of the first bandpass stage 70

106 First low-pass capacitor of the first low-pass circuit of the firstbandpass stage 70

107 First low-pass resistor of the first low-pass circuit of the firstbandpass stage 70

108 Second low-pass capacitor of the second low-pass circuit of thefirst bandpass stage 70

109 Second low-pass resistor of the second low-pass circuit of the firstbandpass stage 70

110 First field effect transistor of the input stage of the convertercircuit 23 and 128

111 Second field effect transistor of the input stage of the convertercircuit 23 and 128

112 First constant current source of the converter circuit 23 and 128

113 First terminal of the first constant current source 112 of theconverter circuit 23 and 128

114 Second terminal of the first constant current source 112 of theconverter circuit 23 and 128

115 Second output terminal of the input stage of the converter circuit23 and 128

116 First output terminal of the input stage of the converter circuit 23and 128

117 First field effect transistor of the first current mirror stage 117,118 of the converter circuit 23 and 128

118 Second field effect transistor of the first current mirror stage117, 118 of the converter circuit 23 and 128

119 Output terminal of the first current mirror stage 117, 118 of theconverter circuit 23 and 128

120 First field effect transistor of the second current mirror stage120, 121 of the converter circuit 23 and 128

121 Second field effect transistor of the second current mirror stage120, 121 of the converter circuit 23 and 128

122 Output terminal of the second current mirror stage 120, 121 of theconverter circuit 23 and 128

123 First field effect transistor of the third current mirror stage 123,124 of the converter circuit 23 and 128

124 Second field effect transistor of the third current mirror stage123, 124 of the converter circuit 23 and 128

125 Output terminal of the third current mirror stage 123, 124 of theconverter circuit 23 and 128

126 Current node (subtraction circuit) of the converter circuit 23 and128

127 Output driver circuit of the converter circuit 23 and 128

128 Improved converter circuit

129 First cascode field effect transistor of the improved convertercircuit 128

130 First field effect transistor of the first cascaded stage of theauxiliary switch-off stage of the improved converter circuit 128

131 Input transistor of the fourth current mirror stage 131, 133 of theauxiliary switch-off stage of the improved converter circuit 128

132 Second cascode field effect transistor in the input arm of thefourth current mirror stage 131, 133 of the auxiliary switch-off stageof the improved converter circuit 128

133 Output transistor of the fourth current mirror stage 131, 133 of theauxiliary switch-off stage of the improved converter circuit 128

134 First field effect transistor of the cascode-bias-voltage generationstage of the improved converter circuit 128

135 Second field effect transistor of the cascode-bias-voltagegeneration stage of the improved converter circuit 128

136 Second constant current source of the cascode-bias-voltagegeneration stage of the improved converter circuit 128

1. A differential oscillator circuit for generating a high-frequencyelectromagnetic oscillation, comprising: an amplifier configuration withtwo inputs and two outputs, an oscillator crystal connected to theoutputs of the amplifier configuration, a bandpass filter configurationwith two inputs and two outputs, which is connected, with inputs, to theoscillator crystal and the two outputs of the amplifier configurationconnected to the oscillator crystal, and back coupled, with two outputs,to the inputs of the amplifier configuration, wherein, throughdimensioning of the amplitude-frequency characteristic or thephase-frequency characteristic of the bandpass filter configuration as afunction of the amplitude-frequency characteristic and thephase-frequency characteristic of the amplifier configuration and theoscillator crystal, the oscillation condition is fulfilled exclusivelyfor a selected harmonic of the oscillator crystal, and thehigh-frequency, electromagnetic oscillation formed by this selectedharmonic of the oscillator crystal is available at the output of thebandpass filter configuration.
 2. An oscillator circuit as claimed inclaim 1, wherein the amplifier configuration is designed with, in eachcase, at least one pair of at least substantially symmetrical inputs andoutputs for processing electromagnetic oscillations, operated at leastsubstantially symmetrically relative to a first reference potential. 3.An oscillator circuit as claimed in claim 2, wherein the amplifierconfiguration comprises a differential amplifier circuit, which isequipped with two field effect transistors coupled at their sourceterminals, the gate terminals of which are each coupled with one of thedifferential inputs of the amplifier configuration, wherein a drainterminal of each field effect transistor forms one of the differentialoutputs of the amplifier configuration, each of which is furthercoupled, via a load path, which comprises at least one field effecttransistor, designated an output load transistor, with a terminalcarrying a second reference potential.
 4. An oscillator circuit asclaimed in claim 3, wherein the amplifier configuration comprises acontrol-voltage generation stage for generating a control voltage, whichis supplied to gate terminals of the output load transistors.
 5. Anoscillator circuit as claimed in claim 4, wherein the control-voltagegeneration stage comprises a series circuit comprising a constantcurrent source and a field effect transistor bridged between its drainterminal and gate terminal.
 6. An oscillator circuit as claimed in claim5, wherein the amplifier configuration comprises an operating-pointregulating stage with three field effect transistors, a first of whichis disposed in the first load path and a second of which is disposed inthe second load path, each connected in series with the output loadtransistor there, and a third of which is connected in series with theseries circuit comprising the constant current source and field effecttransistor of the control-voltage generation stage, wherein a gateterminal of the first of the three field effect transistors of theoperating-point regulating stage is connected to a first of thedifferential outputs of the amplifier configuration, wherein a gateterminal of the second of the three field effect transistors of theoperating-point regulating stage is connected to a second of thedifferential outputs of the amplifier configuration, wherein a gateterminal of the third of the three field effect transistors of theoperating-point regulating stage is connected to the gate terminals ofthe output load transistors and wherein the three field effecttransistors of the operating-point regulating stage are routed, withtheir source terminals, to the terminal carrying the second referencepotential.
 7. An oscillator circuit as claimed in claim 3, wherein theamplifier configuration comprises an offset compensation devicecomprising, in each case, a high-pass circuit between: each of thedifferential inputs of the amplifier configuration, the gate terminal ofthe field effect transistor of the differential amplifier circuitcomprising the amplifier configuration that is coupled with thisdifferential input, the differential output formed by the drain terminalof said field effect transistor, wherein the limiting frequency is smallas compared with the frequency operating range of the oscillatorcircuit.
 8. An oscillator circuit as claimed in claim 7, wherein each ofthe high-pass circuits contains a capacitor, via which the differentialinput of the amplifier configuration is coupled with the gate terminalof the field effect transistor of the differential amplifier circuitcomprising the amplifier configuration, and each of the high-passcircuits further contains an ohmic resistance element, via which thegate terminal of the field effect transistor of the differentialamplifier circuit comprising the amplifier configuration is coupled withthe differential output of the amplifier configuration formed by thedrain terminal of the field effect transistor.
 9. An oscillator circuitas claimed in claim 3, wherein the amplifier configuration is coupledwith an auxiliary starting circuit, by means of which, during apredetermined period when the oscillator circuit is put into operation,a differential voltage is supplied to the gate terminals of the fieldeffect transistors, coupled at their source terminals, of thedifferential amplifier circuit comprising the amplifier configuration.10. An oscillator circuit as claimed in claim 9, wherein the auxiliarystarting circuit preferably comprises: a first field effect transistor,which is disposed between the gate terminal of a first of the fieldeffect transistors, coupled at their source terminals, of thedifferential amplifier circuit comprising the amplifier configuration,and a third reference potential; a second field effect transistor, whichis disposed between the gate terminal of a second of the field effecttransistors, coupled with their source terminals, of the differentialamplifier circuit comprising the amplifier configuration, and the thirdreference potential; a start-signal input for supplying an at leastlargely pulse-shaped or step-shaped start signal when the oscillatorcircuit is put into operation; a delay stage; wherein the start-signalinput is directly coupled with a gate terminal of the first field effecttransistor of the auxiliary starting circuit and, via the delay stage,with a gate terminal of the second field effect transistor of theauxiliary starting circuit.
 11. An oscillator circuit as claimed inclaim 2, wherein the oscillator crystal takes the form of a two-terminalnetwork and is connected with, in each case, one of its terminals to, ineach case, one of the outputs of a pair of differential outputs of theamplifier configuration, in order to supply an electromagneticoscillation emitted by the amplifier configuration in the form of adifferential signal.
 12. An oscillator circuit as claimed in claim 1,wherein the bandpass filter configuration is connected, with at leastone pair of its differential inputs, to at least the pair ofdifferential outputs of the amplifier configuration that are connectedto the terminals of the oscillator crystal, and, with at least one pairof its differential outputs, to at least one pair of differential inputsof the amplifier configuration.
 13. An oscillator circuit as claimed inclaim 12, wherein the bandpass filter configuration is designed with acascade connection of at least two bandpass stages.
 14. An oscillatorcircuit as claimed in claim 13, wherein the bandpass stages aredesigned, each with a differential amplifier circuit having two fieldeffect transistors coupled at their source terminals, and with one pairof differential inputs and one pair of differential outputs, whereineach one of the differential inputs is coupled, via one of the high-passcircuits, with one of the gate terminals of one of the field effecttransistors, and each one of the drain terminals of the field effecttransistors forms one of the differential outputs of the bandpassstages, each of which drain terminal is further connected, via one ofthe low-pass circuits, to a terminal carrying a fifth referencepotential, wherein the differential inputs of a first of the bandpassstages disposed in a cascade connection form the differential inputs ofthe bandpass filter configuration that are connected to the terminals ofthe oscillator crystal, and wherein the differential outputs of a lastof the bandpass stages disposed in a cascade connection form thedifferential outputs of the bandpass filter configuration that areconnected to the differential inputs of the amplifier configuration. 15.An oscillator circuit as claimed in claim 14, wherein the high-passcircuits or the low-pass circuits take the form of RC networks.
 16. Anoscillator circuit as claimed in claim 15, wherein the RC networks areequipped with switchable ohmic resistors.
 17. An oscillator circuit asclaimed in claim 16, comprising a trimming circuit to trim theresistance values of the switchable ohmic resistors in the RC networkswith a reference resistor.
 18. An oscillator circuit as claimed in claim1, comprising a converter circuit, coupled with at least one pair ofdifferential outputs of the bandpass filter configuration, forconverting the differential signal emitted by these differential outputsinto an electromagnetic oscillation operated asymmetrically relative toa reference potential.
 19. An oscillator circuit as claimed in claim 18,wherein the converter circuit comprises: an input stage designed as adifferential amplifier with field effect transistors coupled at theirsource terminals, to which the differential signal to be converted issupplied; a first current mirror stage designed with field effecttransistors coupled via their gate terminals, to mirror a firstdifferential output signal of the input stage of the converter circuitinto a first intermediate signal; a second current mirror stage designedwith field effect transistors coupled via their gate terminals, tomirror a second differential output signal of the input stage of theconverter circuit into a second intermediate signal; a third currentmirror stage designed with field effect transistors coupled via theirgate terminals, to mirror the first intermediate signal of the firstcurrent mirror stage of the converter circuit into a third intermediatesignal; a subtraction circuit, designed as a current node, to subtractthe second intermediate signal from the third intermediate signal; anoutput driver circuit; wherein the third current mirror stage is furthercoupled with: an auxiliary switch-on stage with a first cascode fieldeffect transistor in the input arm of the third current mirror stage; anauxiliary switch-off stage, comprising: a first cascaded stage with aseries circuit comprising: a first field effect transistor, which isincorporated into the second current mirror stage and which is operated,jointly with the second current mirror stage, by the second differentialoutput signal of the input stage of the converter circuit, to emit afourth intermediate signal, which is, at least over segments,essentially proportional to the second intermediate signal; an inputtransistor, designed as a field effect transistor, of a fourth currentmirror stage; a second cascode field effect transistor in the input armof the fourth current mirror stage; the fourth current mirror stage tomirror the fourth intermediate signal into a fifth intermediate signaland to supply it to the third current mirror stage, comprising: theinput transistor, designed as a field effect transistor, to supply thefourth intermediate signal; an output transistor, designed as a fieldeffect transistor, to emit the fifth intermediate signal; and wherein acascode-bias-voltage generating circuit is provided to supply a commoncascode bias voltage to gate terminals, coupled together, of the firstand second cascode field effect transistors.
 20. An oscillator circuitas claimed in claim 19, wherein the cascode-bias-voltage generatingcircuit comprises a series circuit comprising a first and a second fieldeffect transistor and a constant current source, which is disposedbetween a terminal carrying a sixth reference potential and a terminalcarrying a seventh reference potential, wherein this first field effecttransistor is connected, with its drain terminal, to a source terminalof the second field effect transistor, and gate terminals of this firstand this second field effect transistor are connected to each other, toa drain terminal of the second field effect transistor and to the gateterminals of the first and the second cascode field effect transistorsto supply the common cascode bias voltage.